1. Field of the Invention
The disclosure relates in general to systems and methods for memory access. In particular, the disclosure relates to memory access in a configurable memory system.
2. Description of the Related Art
A modern microprocessor system usually comprises a memory system to fulfill CPU memory requests. Conventional memory systems only have fixed functionality, such as directly addressable memory (DAM) to provide a fast and deterministic access time, or cache to provide a local copy of external, off chip memory.
When complexity of the microprocessor system is low, the fixed functionality of the memory system can be designed or planned in the early stage of the design cycle to satisfy functional requirements. However, with increased complexity of microprocessor system, the fixed architecture is not only inflexible but also fails to meet system requirements. Thus, a configurable memory system with combined functionality is utilized to conquer the problem. If the performance of the microprocessor system depends largely on real-time response, the memory system can be configured as more DAM than cache. Otherwise, if the microprocessor system has good spatial and temporal locality in memory access, the memory system can be configured as more cache than DAM.
FIG. 1 shows a conventional circuit controlling selection of cache or directly addressable memory as disclosed in U.S. Pat. No. 6,606,686 to Agarwala, et al.
A memory device comprises 128 sets of 4 ways each and a cache entry size of 128 bytes. Each set, such as set Si 114, includes four cache entries 126, 136, 146 and 156. Each cache entry has a corresponding set of address tag bits and control bits. In FIG. 1, address tag bits 120 and control bits 123 correspond to cache entry 126, address tag bits 130 and control bits 133 correspond to cache entry 136, address tag bits 140 and control bits 143 correspond to cache entry 146, and address tag bits 150 and control bits 153 correspond to cache entry 156.
Each of the address tag bits 120, 130, 140 and 150 has a corresponding address comparison circuit 121, 131, 141 and 151. The address comparison circuits 121, 131, 141 and 151 compare the most significant bits 113 of address 110 with the corresponding address tag bits 120, 130, 140 and 150. Address tag bits 120, 130, 140 and 150 are loaded with the most significant bits of the address of the data cached in the corresponding cache entries 126, 136, 146 and 156. If one of the address comparison circuits 121, 131, 141 or 151 finds a match, this indicates a cache hit, thus AND gates 122, 132, 142 and 152 pass the match signal and indicate the cache hit. Data corresponding to the address to be accessed is stored in the corresponding cache entry 126, 136, 146 or 156. The memory device is then enabled to access data stored in the corresponding cache entry. Thus, the central processing unit can access data for read or write without requiring data transfer to or from the main memory.
In addition, the memory device may be configured as directly addressable memory on the basis of cache ways. Consider the example of one cache way of four configured as directly addressable memory. The cache entry 126 is configured as directly addressable memory, and therefore, AND gate 122 is blocked from passing the match signal from address compare circuit 121 indicating a cache hit due to the 1 on its inverting input while AND gates 132, 142 and 152 are enabled to pass a match signal indicating a cache hit from respective address compare circuits 131, 141 and 151. Accordingly, cache entry 126 is never accessed as cache because the corresponding address tag bits 120 can never generate a cache hit signal. Zero detect circuit 115 and bank select circuit 116 may enable selection of cache entry 126. If middle bits 112 select set Si 114, bits 14 and 15 enable access to cache entry 126 if they are “00”, bank select circuit 116 is enabled. In this example, bank select circuit 116 enables cache entry 126. Then the least significant bits 111 point to one byte of the 128 bytes within cache entry 126. Thus, the address selects a physical location within the memory device corresponding to the received address.
However, there are often several memory ways in the configurable memory system. Since the function of each way varies in different modes, it may be accessed in one mode rather than others. In FIG. 1, address comparison circuits 121, 131, 141 and 151 respectively compare address tag bits 120, 130, 140 and 150 even when a part of the memory device, the cache entry 126, is configured as DAM. Although the comparison result is blocked by AND gates 122 without influencing circuit operation, power consumption is caused by unnecessary comparison.
In addition, as the memory device is configured as cache, the setting of the control registers may be altered during runtime, resulting in control registers differencing between in the memory access cycle and tag comparison cycle. This may cause wrong cache hit detection and the following cache fill operations error.